NAND flash memories and the like are provided with a page buffer (also referred to as a cache memory or a data latch) in addition to a cell array. One-page data read from and written in the cell array is stored in the page buffer.
Column decoders are connected to a page buffer. The column decoders take time for operation, so that it is required to secure a cycle time to the page buffer. For this reason, a method often adopted is an interleave method for accessing a page buffer logically divided into a plurality of areas, when data to each divided area (referred to as a divided page buffer area, hereinafter) is ready.
Access to a cell array is made for each page, and if a column address is a defective address, it is replaced with a redundant column.
In the known interleave method, if there is a defective column in one interleave period, access is made not to a divided page buffer area including the defective column but to another divided page buffer area. Therefore, there is a problem in that, for example, even if originally 5 interleave should be performed, 3 interleave is performed if there are defective columns in two divided page buffer areas, which leads to decrease in interleave efficiency, and hence high-speed data input/out to/from a page buffer cannot be achieved.